1. Field of the Invention
The present invention relates to a synchronizing signal generating circuit, and more particularly, to a synchronizing signal generating circuit which outputs an internal synchronizing signal having the same frequency and phase as reference signal (a Phase Locked Loop circuit: PLL circuit, or a phase synchronizing loop circuit).
2. Description of the Related Art
FIG. 1 is a block diagram showing a configuration of conventional PLL circuit 100. As shown in FIG. 1, PLL circuit 100 comprises phase detector 101, charge pump 102, loop filter (LPF) 103, voltage controlled oscillator 104, lock detector 105, and current generator 106. Japanese Patent Application Laid-Open No. 30417/95 is herein referred to as a prior art example.
Phase detector 101 compares reference signal REF inputted from the outside thereof with internal synchronizing signal OSC. When there is a difference between their frequencies or phases, the phase difference is inputted to charge pump 102 as an UP or DOWN signal.
Charge pump 102 switches on or off PMOS transistor 112 based on an UP signal from phase detector 101, and leads a current from current source 111 to LPF 103. Charge pump 102 also switches on or off NMOS transistor 113 based on a DOWN signal from phase detector 101, and cuts current source 114 out of LPF 103.
LPF 103 operates in a manner such that capacitor 122 is charged and discharged by charge pump 102 and LPF 103 outputs control voltage VCNT. When both MOS transistors 112 and 113 of charge pump 102 are OFF, the electric charge having been charged in capacitor 122 is retained and control voltage VCNT is kept constant.
VCO 104 outputs internal synchronizing signal OSC in an oscillation frequency corresponding to control voltage VCNT.
By composing a loop with phase detector 101, charge pump 102, LPF 103 and VCO 104, differences in frequencies and phases between reference signal REF and internal synchronizing signal OSC are canceled out, and the frequencies and the phases of internal synchronizing signal OSC and reference signal REF are both locked.
Lock detector 105 detects a locked state by using the difference in the phases between reference signal REF and internal synchronizing signal OSC detected by phase detector 101, and outputs current control signal ICNT.
Current generator 106 controls the currents from current sources 111 and 114 of charge pump 102 in response to current control signal ICNT. For example, if the frequencies and the phases of both internal synchronizing signal OSC and reference signal REF are not locked, the current is increased, and decreased if otherwise.
Another method has also been proposed which switches a configuration of LPF 103 corresponding to the difference in the phases between reference signal REF and internal synchronizing signal OSC detected by phase detector 101. FIG. 2 is a diagram showing a circuit configuration of switching LPF 200.
In an unlocked state, only capacitor 202 becomes effective by making switch 203 and 206 ON and OFF respectively. In this manner, a fluctuation in control voltage VCNT becomes large. Meanwhile, in the locked state, the fluctuation in control voltage VCNT is made small by making switch 206 ON and connecting capacitor 205.
By increasing the current charging into or discharging from capacitor 122 and making the change in control voltage VCNT greater, a lock-up time can be shortened.
Furthermore, by decreasing the current and making the fluctuation in control voltage VCNT small, a fluctuation (jitters) in oscillation frequency appearing after the locked state has been established can be reduced.
However, the conventional PLL circuits in the above have problems which will be described below.
As a first problem, in PLL circuit 100, in the case where charge and discharge from charge pump 102 to LPF 103 is carried out by current sources 111 and 114, a noise shown in FIG. 3 is generated in control voltage VCNT due to an effect caused by the gate-drain capacities of PMOS transistor 112 and NMOS transistor 113 when they are switched on and off. FIG. 3 shows waveforms of UP signal, DOWN signal and an output current from the charge pump.
As has been described above, the method has been proposed which switches the configuration of LPF in response to the locked state between reference signal REF and internal synchronizing signal OSC. However, this method also has a problem which will be described below.
In this method, LPF switches 203 and 206 are connected in the manner shown in FIG. 2. In the unlocked state, switch 203 is ON and switch 206 is OFF.
When reference signal REF is locked to internal synchronizing signal OSC, which makes switch 206 become ON, an electric charge having been stored in capacitor 202 flows into capacitor 205 until voltages of both capacitors become equal. Therefore, control voltage VCNT decreases. At this time, it is possible that the locked state is canceled. As a result, reduction in the lock-up time cannot be realized.